A Performance Comparison Between Different Approaches for Implementation of FPGA-based Arbiter Physical Unclonable Function 

Volume 7, Issue 1, February 2022     |     PP. 1-21      |     PDF (907 K)    |     Pub. Date: January 20, 2022
DOI: 10.54647/dee47263    95 Downloads     244631 Views  

Author(s)

Swati K. Kulkarni, Applied Electronics Department, Gulbarga University, Gulbarga-585106, India
Vani R. M, University Science Instrumentation Center, Gulbarga University, Gulbarga-585106, India
P. V. Hunagund, University Science Instrumentation Center, Gulbarga University, Gulbarga-585106, India

Abstract
In our daily lives, embedded and Internet of Things (IoT) applications are becoming extremely important. It advised using intellectual property (IP) while developing embedded and IoT applications. Hardware security and electronic component counterfeiting pose a threat to IoT devices and IPs. Another consideration is that today's electronic industry must contend with a slew of security concerns, including IC cloning, reverse engineering, overbuilding, and physical manipulation. PUF is a part of hardware security, utilized for device authentication, IP core protection, and the creation of cryptographic keys. The PUF uses intrinsic properties of IC fabrication variances to deliver an exclusive identifier for every device. PUF inherently provides security properties. Already, many researchers have concluded that arbiter and SRAM PUF architectures are unsuitable for FPGAs because their delay skew is higher than the random manufacturing process variations. The designer should have an accurate understanding of the FPGA platform. We used the Xilinx FPGA to develop and compare three versions of Arbiters PUF: 64-bit Classical Arbiter PUF, 64-bit,128-bit PDL-based Arbiter PUF, and Wide multiplexer-based Arbiter PUF. A comparison was performed based on the design approach, resource consumption, power analysis, and PUF feature.

Keywords
Arbiter PUF, Programable Delay Line, Register Transfer Level (RTL), FPGA-SOC, Simulation, Synthesis, Placement & Routing and Hardware Validation etc.

Cite this paper
Swati K. Kulkarni, Vani R. M, P. V. Hunagund, A Performance Comparison Between Different Approaches for Implementation of FPGA-based Arbiter Physical Unclonable Function  , SCIREA Journal of Electrical Engineering. Volume 7, Issue 1, February 2022 | PP. 1-21. 10.54647/dee47263

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